Hardware Design Verification

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance_

The Role

The Data Accelerator (DACC) team at AMD is seeking a ASIC Design Verification Lead who will be involved in multiple aspects of IP and sub-system verification. This role is an excellent opportunity to work on the next generation technologies that are part of AMD ASICs powering Servers, Machine Learning, Client and Embedded markets. You will join one of the fastest-growing field of Data-Processing units (DPU) rapidly being adopted across the VLSI industry. The industry is moving towards adding custom hardware offload engines to support complex data operations like encryption, authentication, compression, GPU/CPU compute offloads & virtual machines live migration. This is a tremendous opportunity to get in early into a rapidly expanding domain of custom hardware accelerators. The Design Verification (DV) group within this team is responsible for developing a scalable DV flow and environment with emphasis on automation (using AI), power and performance verification (PPV) and emulation support. Our management fosters and encourages continuous technical innovation to showcase success as well as facilitate continuous career development.

The Person

Highly skilled in advanced ASIC Verification Techniques and planning. Eager to learn new designs and implementation techniques.  Enjoys an environment where everyone in the team can grow and develop with sense of global team spirit. Strong analytical thinking and problem-solving skills, excellent attention to detail.

Key Responsibilities

• Meticulously plan IP and Sub-system DV activities.
• Actively drive the Unified Test plan (UTP) with multi sub-system, emulation and Soc DV teams.
• Perceive and deploy industry leading verification methodologies such as UVM(F), formal verification etc.
• Further advance the use of Artificial Intelligence (AI) Large Language Models (LLMs) in DV activities.
• Advanced and scalable UVM(F) test bench development, constraint random UVM test development, regression debug, coverage closure, performance verification etc.
• Take end to end ownership of key features for the projects.
• Reproduce silicon functional bugs in simulations and/or formal verification tools.
• Conduct and participate in code reviews.
• Most importantly guide and motivate junior members of a very talented DV team.
  
  

Preferred Experience

• Extensive hardware verification experience
• Must be proficient in Verilog, System Verilog, C and C++, UVM, and working in Linux and Windows environments
• Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation tools
• Must have excellent programming skills
• Must have exposure to Makefile, some other scripting languages like perl, python, ruby etc. and use of AI.
  
  
  

Academic Credentials

• Bachelors or Masters degree in computer engineering/Electrical Engineering
  
  
  

LOCATION: Markham, ON

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.